Memory devices with dual encapsulation layers and methods of fabrication
摘要
說(shuō)明書(shū)
The deposition process concludes with the formation of hardmask layer 802 on conductive layer 800° C. In some embodiment, hardmask layer 802 is blanket deposited by a PECVD, CVD, or PVD process. In an embodiment, hardmask layer 802 includes a material that has a favorable etch selectivity compared to the ferroelectric materials in material layer stack 800. In some embodiments, hardmask layer 802 includes materials that can be patterned with high fidelity with respect to a masking layer formed on hardmask layer 802, for example SiO2, Si3N4, DLC (Diamond Like Carbon) or Al2O3. In other embodiments, hardmask layer 802 includes a conductive material that is different from the conductive material of the ferroelectric material. In some embodiments it is desirable to deposit hardmask layer 802 to a thickness, T4 that enables patterning of at least the conductive layer 800° C. In other embodiments, hardmask layer 802 may deposited to a thickness T4 that depends on a total thickness of material layer stack 800. T4 may be at least 20 nm. In a different embodiment, hardmask layer 802 includes a bilayer where the bilayer includes a metallic layer and a dielectric on the metallic layer.
In an embodiment, photoresist mask 804 is formed on hardmask layer 802 and is formed by a lithographic process. The photoresist mask 804 includes blocks 804A and 804B. Each block 804A-B is a mask for patterning a discrete memory device, such as for example a ferroelectric memory device.
