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Memory devices with dual encapsulation layers and methods of fabrication

專利號
US12108608B1
公開日期
2024-10-01
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Noriyuki Sato; Debraj Guhabiswas; Tanay Gosavi; Niloy Mukherjee; Amrita Mathuriya; Sasikanth Manipatruni
IPC分類
H10B53/30; H01L49/02
技術領域
etch,electrode,in,conductive,memory,layer,sidewall,dielectric,device,structure
地域： CA CA San Francisco

摘要

An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

說明書

FIG. 10A is a cross-sectional illustration of the structure in FIG. 9A following the process to deposit an encapsulation layer 1000 on memory device 108 and on etch stop layer 113. In the illustrative embodiment, the electrode structure 112 is not exposed to the encapsulation layer 1000. In an embodiment, encapsulation layer 1000 includes an insulator material that provides a hermetic seal for the individual layers in memory device 108 against impacts of downstream processing. Electrical insulator materials that are substantially easy to pattern include silicon and one or more of carbon, nitrogen, and oxygen. Encapsulation layer 1000 may be deposited by a PVD, PECVD, or an ALD process. The deposition process may be conformal on sidewalls 108A of memory device 108.

In other embodiments, encapsulation layer 1000 can also have a profile that is dependent on profile of sidewall 108A. For example, an encapsulation layer 1000 may be advantageously deposited using a PVD process to form a wider portion adjacent to uppermost surface 108B and narrower portion on sidewalls 108A and at the base of memory device 108. Such a deposition technique may be advantageous when sidewall 108A is tapered. Spacer 114 may be deposited to a thickness TEC between 5 nm and 30 nm. The thickness TEC depends on a maximum spacing, SMI, between adjacent memory devices 108.

In some embodiments, where WES is greater than WMD, the encapsulation layer 1000 is also deposited on an uppermost surface of the encapsulation layer 1000.

權利要求

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