A plasma etch process is utilized to etch the dielectric 138 to form opening 1004. The etch exposes an uppermost surface the logic region 101B of the memory device 108. In the illustrative embodiment, the openings 1004 are tapered. In other embodiments, openings 1004 are substantially vertical. The openings 1004 have a depth DV. DV will depend on TMD and on a thickness of the dielectric 138.
FIG. 10D is a cross-sectional illustration of the structure in FIG. 10C following the process to remove the mask 1002 and deposit a conductive material to form via electrodes 116. In an embodiment, one or more liner layers are formed in opening 1004 on the uppermost layer of memory device 108. In some embodiments, a fill metal such as copper, tungsten, nickel, cobalt is deposited on a liner layer. The liner layer may include ruthenium or tantalum. A planarization process may be performed to remove the excess conductive material deposited on dielectric 138. In an embodiment, the planarization process includes a chemical mechanical polish (CMP) process.
