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Memory devices with dual encapsulation layers and methods of fabrication

專利號
US12108608B1
公開日期
2024-10-01
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Noriyuki Sato; Debraj Guhabiswas; Tanay Gosavi; Niloy Mukherjee; Amrita Mathuriya; Sasikanth Manipatruni
IPC分類
H10B53/30; H01L49/02
技術(shù)領(lǐng)域
etch,electrode,in,conductive,memory,layer,sidewall,dielectric,device,structure
地域： CA CA San Francisco

摘要

An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

說明書

FIG. 20 illustrates architecture 2000 of the coherent cache or memory-side buffer chiplet (e.g., 2007) with multiple controllers and multiple cache banks, in accordance with some embodiments. In some embodiments, architecture 2000 comprises channels (e.g., ch0 2015-1 and ch1 2015-2), cache banks 2001, local cache controller 2002, non-volatile (NV) controller 2003, and reliability logic 2004. Coherent cache or memory-side buffer chiplet 2007 may function as a cache or memory buffer. In some embodiments, cache lookups can map a large physical memory into a small physical cache using indirection via tags. Here, indirection refers to the use of tags to specify which address maps to which physical location. If multiple addresses can map to a single physical location, a tag is used to figure out which address is currently mapped.

In some embodiments, each cache bank 2001 includes data bank 2005 (e.g., comprising memory cells) and associated tags 2006. In some embodiments, data bank 2005 comprises ferroelectric memory cells. In some embodiments, data bank 2005 comprises one or more of: FE-SRAM, FE-DRAM, SRAM, MRAM, resistance RAM (Re-RAM), embedded DRAM (e.g., 1T-1C based memory), or a combination of them. Using FE-SRAM, MRAM, or Re-RAM allows for low power and high-speed memory operation. In some embodiments, when data bank 2005 includes ferroelectric memory, it uses NV controller 2003 and a stronger reliability logic (e.g., error correction code) for security compared to non-ferroelectric memory for data bank 2005.

權(quán)利要求

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