The second wireless device 200 may include one or more processors 202 and one or more memories 204 and additionally further include one or more transceivers 206 and/or one or more antennas 208. The processor(s) 202 may control the memory(s) 204 and/or the transceiver(s) 206 and may be configured to implement the descriptions, functions, procedures, suggestions, methods and/or operational flowcharts described in the present disclosure. For example, the processor(s) 202 may process information within the memory(s) 204 to generate third information/signals and then transmit radio signals including the third information/signals through the transceiver(s) 206. The processor(s) 202 may receive radio signals including fourth information/signals through the transceiver(s) 106 and then store information obtained by processing the fourth information/signals in the memory(s) 204. The memory(s) 204 may be connected to the processor(s) 202 and may store a variety of information related to operations of the processor(s) 202. For example, the memory(s) 204 may store software code including commands for performing a part or the entirety of processes controlled by the processor(s) 202 or for performing the descriptions, functions, procedures, suggestions, methods and/or operational flowcharts described in the present disclosure. Herein, the processor(s) 202 and the memory(s) 204 may be a part of a communication modem/circuit/chip designed to implement RAT (e.g., LTE or NR). The transceiver(s) 206 may be connected to the processor(s) 202 and transmit and/or receive radio signals through one or more antennas 208. Each of the transceiver(s) 206 may include a transmitter and/or a receiver. The transceiver(s) 206 may be interchangeably used with RF unit(s). In the present disclosure, the second wireless device 200 may represent a communication modem/circuit/chip.