In embodiments of the present disclosure, T6 may be a double-gate transistor to reduce its leakage current and adequately maintain the potential of the gate electrode of T1, but the present disclosure is not limited to this.
FIG. 2 is an operating timing diagram of the example of the pixel driving circuit shown in FIG. 1, in which t1 is a first stage, t2 is a second stage, t3 is a third stage, and the data voltage provided by the data line Data(n) the data voltage is labeled as Vdata.
As shown in FIG. 2, when the example of the pixel driving circuit shown in FIG. 1 is in operation,
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- in the first stage t1 (i.e. a reset stage), Reset(n) inputs a low electrical level, G(n) inputs a high electrical level, EM(n) inputs a high electrical level, T6 is on, and the potential of the gate electrode of T1 is reset to the initial voltage;