Thereafter, as shown in FIG. 3, forming a conformal liner layer 120 on the surface of MRAM cells 118 and inter-layer dielectric layer 106, wherein the material of liner layer 120 preferably includes silicon nitride. However, other dielectric materials may also be selected, such as silicon oxide, silicon oxynitride or silicon oxide carbides, depending on process requirements. Next, a dielectric layer 122, a stop layer 124 and an inter-metal dielectric 126 are sequentially formed on the liner layer 120. The dielectric layer 122 would fill up the gap between the MRAM cells 118 and be planarized by using planarization process such as chemical mechanical polishing (CMP), so that it's top surface would be level with or slightly higher than the MRAM cells 118. In the embodiment of present invention, the material of dielectric layer 122 and inter-metal dielectric 126 is preferably ultra low-k material, and the material of stop layer 124 is preferably nitrogen doped carbide, silicon nitride or silicon carbonitride (SiCN).