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Semiconductor memory device and fabrication method thereof

專利號
US12133479B2
公開日期
2024-10-29
申請人
UNITED MICROELECTRONICS CORP.（TW Hsin-Chu）
發(fā)明人
Chia-Ching Hsu
IPC分類
H01L45/00; H10N70/00; H10N70/20
技術(shù)領(lǐng)域
layer,dielectric,electrode,top,te,in,metal,teu,resistive,conductive
地域： Hsin-Chu

摘要

A semiconductor memory device includes a substrate, a first dielectric layer on the substrate, a bottom electrode on the first dielectric layer, a second dielectric layer on the first dielectric layer, and a top electrode in the second dielectric layer. The top electrode has a lower portion around the bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrode and around the tapered upper portion of the top electrode. A resistive-switching layer is disposed between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode. An air gap is disposed in the third dielectric layer.

說明書

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to the field of semiconductor technology, in particular to a resistive random access memory device (RRAM) and a manufacturing method thereof.

2. Description of the Prior Art

Resistive RAM (RRAM) is a general name for two-terminal reprogrammable devices that can be set to either a low or high resistance state. RRAM generally consists of a dielectric layer disposed between two electrodes. Some types of RRAM conduct by forming a distinct filament in a limited area of the dielectric. Other types of RRAM conduct by changing the properties of the dielectric throughout its area.

RRAM stores data by using the variable resistance characteristic of a dielectric layer interposed between two electrodes. Such dielectric layer, as a resistive layer, is normally insulating but can be made to be conductive through a filament or conduction path formed after application of a sufficiently high voltage, i.e. through a forming process. The conduction path formation can arise from different mechanisms, including defects, metal migration, etc. Once the filament is formed, it may be reset (i.e. broken, resulting in high resistance) or set (i.e. re-formed, resulting in lower resistance) by an appropriately applied voltage.

The high-density RRAM structure is usually formed in the back-end metallization process (BEOL), which leads to higher parasitic capacitance and RC delay. Therefore, there is still a need for an improved RRAM structure in this technical field, which can improve the parasitic capacitance problem.

SUMMARY OF THE INVENTION

權(quán)利要求

1
What is claimed is:1. A semiconductor memory device, comprising:a substrate;a first dielectric layer on the substrate;a bottom electrode on the first dielectric layer;a second dielectric layer on the first dielectric layer;a top electrode in the second dielectric layer, wherein the top electrode comprises a lower portion around the bottom electrode and a tapered upper portion;a third dielectric layer above the bottom electrode and around the tapered upper portion of the top electrode;a resistive-switching layer between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode; andan air gap in the third dielectric layer.2. The semiconductor memory device according to claim 1 further comprising:a dielectric block layer between the second dielectric layer and the first dielectric layer.3. The semiconductor memory device according to claim 2, wherein the top electrode is disposed on the dielectric block layer.4. The semiconductor memory device according to claim 1, wherein the resistive-switching layer comprises NiOx, TayOx, TiOx, HfOx, WOx, ZrOx, AlyOx, SrTiOx, NbyOx, or YyOx, wherein x>0, y>0.5. The semiconductor memory device according to claim 1, wherein the top electrode comprises TiN, TaN or Pt.6. The semiconductor memory device according to claim 1, wherein a top surface of the second dielectric layer is coplanar with a top surface of the top electrode.7. The semiconductor memory device according to claim 1 further comprising:a metal layer disposed in the third dielectric layer and electrically connected to the top electrode.8. The semiconductor memory device according to claim 1, wherein a top surface of the third dielectric layer is coplanar with a top surface of the top electrode and a top surface of the second dielectric layer.9. The semiconductor memory device according to claim 8 further comprising:a capping layer covering the second dielectric layer, the top electrode and the third dielectric layer;a fourth dielectric layer on the capping layer; anda conductive via disposed in the fourth dielectric layer and electrically connected to the top electrode.10. The semiconductor memory device according to claim 1, wherein a thickness of the tapered upper portion of the top electrode is greater than a thickness of the lower portion of the top electrode.
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