According to an embodiment of the present invention, on the dielectric barrier layer BL and between the bottom electrode BE in the middle and the bottom electrode BE on the right, a plurality of top electrodes TE may be arranged at intervals along the second direction D2. According to an embodiment of the present invention, the plurality of top electrodes TE may be approximately equidistantly arranged and aligned in the second direction D2. According to the embodiment of the present invention, the top electrodes TE are located in the second dielectric layer 120. As shown in FIG. 1, in the second direction D2, the second dielectric layer 120 is disposed between the top electrodes TE.

According to an embodiment of the present invention, each of the top electrodes TE includes a lower portion TEB and a tapered upper portion TEU. The lower portion TEB is located around the bottom electrode BE. The tapered upper portion TEU of the top electrode TE gradually decreases in width from top to bottom, and is connected to the lower TEB with approximately the same width. According to an embodiment of the present invention, the thickness t₁ of the tapered upper portion TEU of the top electrode TE is greater than the thickness t₂ of the lower portion TEB of the top electrode TE. According to an embodiment of the present invention, the top electrode TE may include TiN, TaN, or Pt, but is not limited thereto. According to an embodiment of the present invention, the top surface 120s of the second dielectric layer 120 is flush with the top surface TES of the top electrode TE.