Please refer to FIG. 1 and FIG. 2. FIG. 1 is a top view of a part of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line I-I′ in FIG. 1. As shown in FIG. 1 and FIG. 2, the semiconductor memory device 1 includes a substrate 100, such as a semiconductor substrate, but is not limited thereto. The substrate 100 may include a memory array area MA and a logic circuit area LA. The semiconductor memory device 1 further includes a first dielectric layer 110 on the substrate 100 and covering the memory array area MA and the logic circuit area LA. According to an embodiment of the present invention, the first dielectric layer 110 may include a silicon oxide layer, but is not limited thereto. According to an embodiment of the present invention, a metal layer 112, such as a copper metal layer, but is not limited thereto, may be formed in the first dielectric layer 110. According to the embodiment of the present invention, for example, the metal layer 112 may be the third metal layer (M3) in the metal interconnection structure, but is not limited thereto. According to an embodiment of the present invention, a dielectric barrier layer BL, such as a silicon nitride layer, may be formed on the first dielectric layer 110. A plurality of openings BLO may be formed in the dielectric barrier layer BL, which respectively expose the top surfaces of the corresponding metal layers 112.