Reducing qubit frequency collisions through lattice design
地域：
NY
NY Armonk
摘要
Lattice arrangements for quantum qubits are described. A lattice arrangement can comprise adjacent structures having vertices connected by edges. The qubits can be positioned on the vertices. A qubit in the lattice arrangement directly connects to not more than three other qubits, or connects to another qubit via a coupling qubit on an edge between two qubits on a vertex. The adjacent structures can comprise hexagons, dodecagons or octagons. A superconducting qubit lattice can comprise superconducting target qubits and superconducting control qubits. The superconducting qubit lattice can comprise adjacent structures having vertices connected by edges, with target qubits positioned on the vertices and control qubits positioned on the edges. Logic operations between adjacent superconducting target and control qubits can be implemented by driving the superconducting control qubit at or near the frequency of the superconducting target qubit.
說(shuō)明書
The subject disclosure relates generally to quantum computing, and more particularly to a lattice arrangement of qubits for quantum computations.
Quantum information processing (quantum computing) holds the potential for solving certain categories of mathematical problems that are intractable with conventional machine computations. Quantum computing employs quantum physics to encode information; for example, a quantum computer can employ quantum bits (qubits), which are basic units of quantum information, and thus a quantum computer can employ qubits to encode information. Building a highly useful quantum computer will need to have likely on the order of millions of physical qubits.
Many conventional quantum computer architectures are arranged with the physical qubits coupled vertically and horizontally to nearest neighbor qubits, forming a two-dimensional grid. However, the frequencies of qubits are not well controllable in some physical systems implementing qubits, and in practice, qubits have a spread in frequency due to imperfections following fabrication. Some ranges of frequencies are such that a gate comprised of two neighboring qubits does not work well, if at all, which is referred to as a frequency collision, which prohibits logical operations between those qubits. In extreme cases the frequency ranges are sufficiently bad such that a useless qubit results, basically resulting in a hole in the lattice.
權(quán)利要求
What is claimed is:1. A quantum processing device comprising:qubits arranged in a lattice arrangement, in which the lattice arrangement comprises:adjacent structures having vertices connected by edges, wherein the qubits are positioned on the vertices, and wherein each of the qubits in the lattice arrangement connects to, thereby being directly adjacent to, with no intervening elements, not more than three other qubits such that a connectivity of each of the qubits to other ones of neighboring qubits, by arranging the qubits with the lattice arrangement, lowers a likelihood of a frequency collision between neighboring ones of the qubits. 2. The quantum processing device of claim 1 , wherein the adjacent structures comprise hexagons. 3. The quantum processing device of claim 1 , wherein the adjacent structures comprise hexagons having qubits on the edges between the vertices of the hexagons. 4. The quantum processing device of claim 1 , wherein the adjacent structures comprise dodecagons. 5. The quantum processing device of claim 1 , wherein the adjacent structures comprise dodecagons having qubits on the edges between the vertices of the dodecagons. 6. The quantum processing device of claim 1 , wherein the adjacent structures comprise octagons. 7. The quantum processing device of claim 1 , wherein the adjacent structures comprise octagons having qubits on the edges between the vertices of the octagons. 8. The quantum processing device of claim 1 , wherein the adjacent structures comprise rectangles having qubits on the edges between the vertices of the rectangles. 9. A superconducting qubit lattice of a quantum processing device, comprising:superconducting target qubits, and superconducting control qubits, in which the superconducting qubit lattice comprises adjacent structures having vertices connected by edges, wherein the superconducting target qubits are positioned on the vertices and the superconducting control qubits are positioned on the edges, and wherein a first superconducting target qubit connects to a second superconducting target qubit via a superconducting control qubit on an edge between the first superconducting target qubit and the second superconducting target qubit, wherein the superconducting control qubits are distinct from the first superconducting target qubit and from the second superconducting target qubit, and wherein the superconducting qubit lattice outputs one or more measurements of the states of the superconducting qubits for feedback to a control device. 10. The superconducting qubit lattice of the quantum processing device of claim 9 , wherein the adjacent structures comprise hexagons having superconducting control qubits on the edges between the vertices of the hexagons. 11. The superconducting qubit lattice of the quantum processing device of claim 9 , wherein the adjacent structures comprise dodecagons having superconducting control qubits on the edges between the vertices of the dodecagons. 12. The superconducting qubit lattice of the quantum processing device of claim 9 , wherein the adjacent structures comprise octagons having superconducting control qubits on the edges between the vertices of the octagons. 13. The superconducting qubit lattice of the quantum processing device of claim 9 , wherein the adjacent structures comprise rectangles having superconducting control qubits on the edges between the vertices of the rectangles. 14. A superconducting qubit lattice of a quantum processing device, comprising: superconducting qubits, in which a lattice arrangement of the superconducting qubit lattice comprises adjacent structures having vertices connected by edges, wherein the superconducting qubits are positioned on the vertices, and in which each of the superconducting qubits connects, and thereby is adjacent to, not more than three other superconducting qubits such that a connectivity of each of the superconducting qubits to other ones of neighboring superconducting qubits, by arranging the superconducting qubits with the lattice arrangement, lowers a likelihood of a frequency collision between neighboring ones of the superconducting qubits, and wherein a first superconducting qubit connects to a second superconducting qubit only via a coupling superconducting qubit on an edge between the first superconducting qubit on a first vertex and the second superconducting qubit on a second vertex. 15. The superconducting qubit lattice of the quantum processing device of claim 14 , wherein the adjacent structures comprise hexagons. 16. The superconducting qubit lattice of the quantum processing device of claim 14 , wherein the adjacent structures comprise dodecagons or octagons. 17. A superconducting qubit lattice, comprising:a group of qubits comprising superconducting target qubits, and superconducting control qubits, in which a lattice arrangement of the superconducting qubit lattice comprises adjacent structures having vertices connected by edges, wherein the superconducting target qubits are positioned on the vertices and the superconducting control qubits are positioned on the edges, wherein a first superconducting target qubit connects to a second superconducting target qubit via a superconducting control qubit on an edge between the first superconducting target qubit and the second superconducting target qubit, wherein the superconducting qubit lattice is adapted to drive the superconducting control qubit at or near the frequency of at least one of the first superconducting target qubit and the second superconducting target qubit, thereby implement a logic operation between the first superconducting target qubit and the second superconducting target qubit, and wherein each of the qubits in the lattice arrangement connects to, thereby being directly adjacent to, with no intervening elements, not more than three other qubits such that a connectivity of each of the qubits to other ones of neighboring qubits, by arranging the qubits with the lattice arrangement, lowers a likelihood of a frequency collision between neighboring ones of the qubits. 18. The superconducting qubit lattice of claim 17 , wherein the adjacent structures comprise hexagons. 19. The superconducting qubit lattice of claim 17 , wherein the adjacent structures comprise dodecagons, or wherein the adjacent structures comprise octagons. 20. The superconducting qubit lattice of claim 17 , wherein the adjacent structures comprise hexagons having superconducting control qubits on the edges between the vertices of the hexagons. 21. The superconducting qubit lattice of claim 17 , wherein the adjacent structures comprise dodecagons having superconducting control qubits on the edges between the vertices of the dodecagons. 22. The superconducting qubit lattice of claim 17 , wherein the adjacent structures comprise octagons having superconducting control qubits on the edges between the vertices of the octagons. 23. The superconducting qubit lattice of claim 17 , wherein the adjacent structures comprise rectangles having superconducting control qubits on the edges between the vertices of the rectangles.
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