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Bit line structure, manufacturing method thereof and semiconductor memory

專利號
US12150293B2
公開日期
2024-11-19
申請人
CHANGXIN MEMORY TECHNOLOGIES, INC.(CN Hefei)
發(fā)明人
ChihCheng Liu
IPC分類
H01L27/108; H10B12/00
技術(shù)領(lǐng)域
bit,line,contact,structure,in,lines,array,first,second,structures
地域: Hefei

摘要

A bit line structure, a manufacturing method thereof, and a semiconductor memory are provided. The bit line structure includes a first bit line array and a second bit line array. The first bit line array includes a plurality of first bit lines extending in a Y direction. The plurality of first bit lines have a same length and are aligned and arranged in an X direction. The second bit line array includes a plurality of second bit lines extending in the Y direction. The plurality of second bit lines have a same length and are aligned and arranged in the X direction. The first bit line array and the second bit line array are not aligned in the X direction. The X direction is perpendicular to the Y direction.

說明書

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

In an embodiment, the first bit line contact structure 111 and the second bit line contact structure 211 each have a rectangular, T-shaped, or semicircular cross-section. The first bit line contact structure 111 and the second bit line contact structure 211 in the embodiment of FIG. 1 are rectangular bit line contact structures. FIG. 4 is a schematic diagram of a T-shaped bit line contact structure according to an embodiment. FIG. 5 is a schematic diagram of a semicircular bit line contact structure according to an embodiment. As shown in FIGS. 1, 4, and 5, the first bit line contact structure 111 and the second bit line contact structure 211 of any cross-sectional shape are suitable for the bit line structure. Therefore, the bit line contact structures of other cross-sectional shapes not shown in the present embodiment are also within the protection scope of the present embodiment.

權(quán)利要求

1
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