The semiconductor memory of the present embodiment is based on the first bit line array 100 and the second bit line array 200 which are not aligned in the X direction. The cross-sectional areas of the first bit line contact structure 111 and the second bit line contact structure 211 are enlarged by providing a larger arrangement space in a horizontal plane for the first bit line contact structure 111 and the second bit line contact structure 211. Therefore, the contact resistance between the first bit line contact structure 111 and the corresponding bit line and the contact resistance between the second bit line contact structure 211 and the corresponding bit line are reduced, and the sensing margin and the charge-discharge speed of the semiconductor memory are improved.

In the description of the disclosure, it is understood that the terms “upper”, “l(fā)ower”, “vertical”, “horizontal”, “inner”, “outer”, etc. indicate orientations or positional relationships based on that shown in the drawings. They are merely intended to facilitate describing the disclosure and to simplify the description rather than indicating or implying that the referenced device or element must have a particular orientation and be constructed and operated in a particular orientation, and are thus not to be construed as limiting the disclosure.

The technical features of the above-described embodiments may be combined arbitrarily. In order to simplify the description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no conflict between these technical features, they should be considered to be within the scope of this specification.