In an embodiment, as shown in FIG. 1, the plurality of first bit lines 110 and the plurality of second bit lines 210 are spaced apart from each other in the X direction. That is, two bit lines adjacent to each first bit line 110 are second bit lines 210, and two bit lines adjacent to each second bit line 210 are first bit lines 110. Compared with the first bit lines 110 and the second bit lines 210 which are not spaced apart from each other, the present embodiment improves the bit line distribution density in the bit line structure, thereby reducing the device area occupied by the bit line structure in the X direction, further improving the integration level of a semiconductor device, and reducing the area of the semiconductor device.

In an embodiment, as shown in FIG. 2, the plurality of first bit lines 110 have first bit line contact structures 111 on a positive side of the Y direction. As shown in FIG. 3, the plurality of second bit lines 210 have second bit line contact structures 211 on a negative side of the Y direction. In another embodiment, the plurality of first bit lines 110 have first bit line contact structures 111 on a negative side of the Y direction. The plurality of second bit lines 210 have second bit line contact structures 211 on a positive side of the Y direction.