Memory layout for reduced line loading
地域：
Hsin-Chu
摘要
Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.
說明書
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
This application is a Continuation of U.S. patent application Ser. No. 16/156,026, filed on Oct. 10, 2018, which claims the benefit of U.S. Provisional Application No. 62/673,233, filed on May 18, 2018. The contents of the above-referenced Patent Applications are hereby incorporated by reference in their entirety.
Many modern day electronic devices include non-volatile memory. Non-volatile memory is electronic memory that is able to store data in the absence of power. Some promising candidates for the next generation of non-volatile memory include resistive random-access memory (RRAM). RRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
權利要求
What is claimed is:1. An integrated circuit (IC) comprising:an array of unit cells comprising a plurality of rows and a plurality of columns, wherein the plurality of columns comprises a first column and a second column; a first conductive wire extending along the first column, wherein the first conductive wire is entirely metal and is electrically coupled to unit cells of the array in the first column; a second conductive wire extending along the second column, wherein the second conductive wire is electrically coupled to unit cells of the array in the second column; and a first conductive bridge directly contacting the first and second conductive wires and being entirely metal; wherein the first conductive bridge, the first conductive wire, and the second conductive wire are spaced from the array of unit cells, wherein the unit cells of the array comprise individual memory structures, wherein the array of unit cells comprises a first unit cell, which comprises a first memory structure and a first access transistor that are electrically coupled together, and wherein the first conductive wire is electrically shorted to a source region of the first access transistor, which is electrically separated from the first memory structure by a channel of the first access transistor. 2. The IC according to claim 1 , wherein the plurality of columns further comprises a third column and a fourth column, wherein the first conductive wire extends along the third column and is electrically coupled to unit cells of the array in the third column, and wherein the second conductive wire extends along the fourth column and is electrically coupled to unit cells of the array in the fourth column. 3. The IC according to claim 1 , further comprising:a plurality of conductive bridges, including the first conductive bridge, wherein the plurality of conductive bridges are evenly spaced along the first column and are entirely metal, and wherein each of the plurality of conductive bridges directly contacts the first and second conductive wires. 4. The IC according to claim 1 , wherein the first conductive bridge is line shaped and extends transverse to the first and second conductive wires. 5. The IC according to claim 1 , wherein the first and second conductive wires extend linearly from a first side of the array to a second side of the array opposite the first side. 6. The IC according to claim 1 , wherein the array of unit cells overlies a semiconductor substrate, and wherein the IC further comprisesa third conductive wire and a conductive via that are vertically stacked in a direction orthogonal to a bottom surface of the semiconductor substrate and that are both elevated relative to the first conductive bridge in the direction, wherein the first memory structure directly overlies the third conductive wire and the conductive via in the direction, and wherein the bottom surface of the semiconductor substrate faces away from the array of unit cells. 7. The IC according to claim 1 , wherein the plurality of rows comprise a first row, wherein the array of unit cells comprises the first unit cell and a second unit cell that are in the first row and that respectively comprise the first access transistor and a second access transistor, and wherein the IC comprises:a continuous word line that is elongated along the first row and that forms individual gate electrodes of the first and second access transistors. 8. The IC according to claim 1 , wherein the array of unit cells overlies a semiconductor substrate, wherein the first and second conductive wires and the first conductive bridge have individual greatest dimensions, which extend parallel to a bottom surface of the semiconductor substrate, and wherein the bottom surface of the semiconductor substrate faces away from the array of unit cells. 9. The IC according to claim 1 , further comprising:a third conductive wire extending along the first column and electrically coupled to the unit cells of the array in the first column, wherein the first memory structure has a first terminal electrically shorted to the third conductive wire and has a second terminal electrically shorted to a drain region of the first access transistor, and wherein the first and third conductive wires have individual greatest dimensions extending in parallel. 10. An integrated circuit (IC) comprising:an array of unit cells comprising individual memory structures overlying and spaced from a semiconductor substrate, and comprising a plurality of rows and a plurality of columns, wherein the plurality of columns comprises a first column and a second column, wherein the plurality of rows comprise a first row, and wherein the array of unit cells comprises a first unit cell and a second unit cell that are in the first row and that respectively comprise a first transistor and a second transistor; a conductive structure electrically coupled to unit cells of the array in the first and second columns, wherein the conductive structure has a pair of column segments elongated respectively along the first and second columns and further has a first bridge segment interconnecting the column segments; and a continuous word line that is elongated along the first row and that forms individual gate electrodes of the first and second transistors; wherein the first bridge segment is laterally and directly between the pair of column segments in a first direction parallel to a bottom surface of the semiconductor substrate, which faces away from the individual memory structures. 11. The IC according to claim 10 , wherein the conductive structure has a ladder-shaped top layout in which the column segments and the first bridge segment respectively define legs of the ladder-shaped top layout and a rung of the ladder-shaped top layout. 12. The IC according to claim 10 , wherein the unit cells of the array are two-transistor one-resistor (2T1R) memory cells. 13. The IC according to claim 10 , wherein the conductive structure repeats periodically along the plurality of rows. 14. The IC according to claim 10 , wherein the pair of column segments have individual top surfaces and individual bottom surfaces, wherein a top surface of the first bridge segment is level with the individual top surfaces of the pair of column segments, and wherein a bottom surface of the first bridge segment is level with the individual bottom surfaces of the pair of column segments. 15. The IC according to claim 10 , wherein the pair of column segments are entirely between the semiconductor substrate and the individual memory structures in a second direction orthogonal to the bottom surface of the semiconductor substrate. 16. The IC according to claim 10 , wherein the individual gate electrodes comprise a first gate electrode of the first transistor, and wherein the first bridge segment overlies the first gate electrode and is elongated along the first row. 17. The IC according to claim 10 , wherein the first bridge segment directly contacts the pair of column segments, and wherein the first bridge segment and the pair of column segments are entirely a single conductive material. 18. An integrated circuit (IC) comprising:an array of transistors over a substrate and comprising a plurality of rows and a plurality of columns, wherein the plurality of columns comprises a first column and a second column; and an interconnect structure covering the array and comprising a plurality of wires and a plurality of vias that are alternatingly stacked; wherein the plurality of wires comprise a first wire and a second wire respectively defining a first conductive column path and a second conductive column path, which extend respectively along the first and second columns, from a first side of the array to a second side of the array opposite the first side, wherein the first and second conductive column paths are spaced from each other and are electrically coupled to transistors of the array respectively in the first and second columns, wherein the interconnect structure further defines a first conductive bridge path extending from the first conductive column path to the second conductive column path, wherein the interconnect structure comprises a single conductive material type continuously from the first conductive bridge path to each of the first and second conductive column paths, and wherein the plurality of vias comprises a first via and a second via extending respectively from direct contact with the first and second wires respectively to direct contact with a first transistor of the array in the first column and a second transistor of the array in the second column. 19. The IC according to claim 18 , wherein the interconnect structure further defines a plurality of conductive bridge paths, including the first conductive bridge path, extending from the first conductive column path to the second conductive column path. 20. The IC according to claim 18 , wherein the plurality of columns comprises a third column and a fourth column, wherein the first conductive column path and the second conductive column path extend respectively along the third and fourth columns, from the first side of the array to the second side of the array, and wherein the first and second conductive column paths are electrically coupled to transistors of the array respectively in the third and fourth columns.
意見反饋