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Memory layout for reduced line loading

專利號
US12156409B2
公開日期
2024-11-26
申請人
Taiwan Semiconductor Manufacturing Co., Ltd.(TW Hsinchu)
發(fā)明人
Chih-Yang Chang; Wen-Ting Chu
IPC分類
H10B63/00; H01L21/768; H01L23/522; H01L23/528; H10N70/00
技術(shù)領(lǐng)域
conductive,bit,source,bridges,lines,702s,line,cells,in,columns
地域: Hsin-Chu

摘要

Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

說明書

As illustrated by the block diagram 200H of FIG. 2H, the source lines 108 are grouped into groups of four, where the groups are non-overlapping and each group comprises four neighboring source lines. For example, source line SL1, source line SL2, source line SL3, and source line SL4 may be grouped. Note that only one group has been illustrated. Further, the conductive bridges 110 each correspond to one of the groups and each electrically couples two source lines in the corresponding group. At each of the groups, the conductive bridges for the group alternate between electrically coupling the first and third source lines of the group and the second and fourth source lines of the group. For example, at a group made up of source line SL1, source line SL2, source line SL3, and source line SL4, conductive bridges in the group may alternate between electrically coupling source line SL1 and source line SL3 and electrically coupling source line SL2 and source line SL4. In some embodiments, the correspondence between the conductive bridges 110 and the groups is many-to-one.

Also illustrated by the block diagram 200H of FIG. 2H, the conductive bridges 110 are evenly spaced, albeit staggered, along the columns and have a one-row pitch. Notwithstanding that FIG. 2H illustrates the conductive bridges 110 with a one-row pitch, two-row pitches, three-row pitches, and other pitches are amenable.

權(quán)利要求

1
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