As illustrated by the top layout 500A of FIG. 5A, the bit cells 102 are respectively on device regions 502d of a semiconductor substrate 502. For ease of illustration, only some of the bit cells 102 are identified. The device regions 502d accommodate source/drain regions (not shown) of the first and second access transistors 304, 306 in FIG. 4B and are separated and demarcated by isolation structures 504. The device regions 502d and the isolation structures 504 extend laterally in a Y direction. The Y direction may, for example, correspond to columns in the array 104 of bit cells. See, for example, columns C1-C4 in FIG. 4B. In some embodiments, the device regions 502d and the isolation structures 504 are line shaped and/or are substantially parallel to each other. Other shapes are, however, amenable. The semiconductor substrate 502 may, for example, be a bulk silicon substrate, some other suitable bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate. The isolation structures 504 may, for example, be shallow trench isolation (STI) structures, deep trench isolation (DTI) structure, or some other suitable isolation structure.
