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Apparatuses and methods for compensating for crosstalk noise at input receiver circuits

專利號(hào)
US12160231B2
公開日期
2024-12-03
申請(qǐng)人
Lodestar Licensing Group LLC
發(fā)明人
Raghukiran Sreeramaneni; Daniel B. Penney
IPC分類
H03K5/00; G11C11/4093; H03K5/01; H03K5/1252; H03K17/687
技術(shù)領(lǐng)域
signal,input,ch0,crosstalk,var,may,circuit,idref,ch1,receiver
地域： IL IL Evanston

摘要

An input receiver circuit for a signal line may receive inputs from other signal lines to mitigate crosstalk noise present on the signal line. In some examples, the input receiver circuit may include a transistor with a programmable width. In some examples, the input receiver circuit may include a bias current generator with a programmable current. The width and/or current may be programmed based on an amount of crosstalk noise introduced by the other signal line. In some examples, the input receiver circuit may include a resistance and/or a capacitance. In some examples the resistor and/or capacitor may be programmable. The resistance and/or capacitance may be programmed based on a duration of the crosstalk noise on the signal line.

說明書

CROSS REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of U.S. Patent Application Ser. No. 17/687,959 filed Mar. 7, 2022 and issued as U.S. Pat. No. 11,683,033 on Jun. 20, 2023, which is a continuation of U.S. patent application Ser. No. 17/160,204 filed Jan. 27, 2021 and issued as U.S. Pat. No. 11,296,693 on Apr. 5, 2022. The aforementioned applications, and issued patents, are incorporated herein by reference, in their entirety, for any purpose.

BACKGROUND

Semiconductor memories are used in many electronic systems to store data that may be retrieved at a later time. As the demand has increased for electronic systems to be faster, have greater data capacity, and consume less power, semiconductor memories that may be accessed faster, store more data, and use less power have been continually developed to meet the changing needs. Part of the development includes creating new specifications for controlling and accessing semiconductor memories, with the changes in the specifications from one generation to the next directed to improving performance of the memories in the electronic systems.

Semiconductor memories are generally controlled by providing the memories with command signals, memory addresses signals, and clocks. The various command and address signals, and clocks may be provided by a memory controller, for example. The command signals may control the semiconductor memories to perform various memory operations, for example, a read operation to retrieve data from a memory, and a write operation to store data to the memory. Data signals may be provided between the controller and memories with known timing relative to receipt by the memory of an associated command.

權(quán)利要求

1
What is claimed is:1. An apparatus comprising:an input receiver circuit configured to:receive a first input signal from a first input signal line and a second input signal from a second input signal line; andgenerate a first mitigation signal based, at least in part, on the second input signal, wherein the first input signal includes at least a portion of the second input signal and the first mitigation signal is configured to cancel at least a portion of the second input signal from the first input signal, wherein the first mitigation signal is based, at least in part, on a third input signal and the first input signal includes at least a portion of the third input signal and the first mitigation signal is further configured to cancel at least a portion of the third input signal from the first input signal.2. The apparatus of claim 1, wherein the first signal line is adjacent to the second signal line.3. The apparatus of claim 1, wherein the third input signal is received by the input receiver from a third input signal line adjacent to the first input signal line.4. The apparatus of claim 1, wherein the input receiver circuit is further configured to generate a second mitigation signal, wherein the second mitigation signal is based, at least in part, on the second input signal and the second mitigation signal is configured to cancel at least a portion of the second input signal from the first input signal.5. The apparatus of claim 1, wherein the first input signal line is capacitively coupled to the second input signal line and the mitigation signal is based, at least in part, on the capacitive coupling of the first input signal line and the second input signal line.6. The apparatus of claim 1, wherein the first input signal line and the second input signal line are data lines.7. The apparatus of claim 1, wherein the input receiver circuit comprises a transistor having a programmable width.8. The apparatus of claim 1, wherein the input receiver circuit comprises a resistance.9. The apparatus of claim 8, wherein the resistance is programmable.10. The apparatus of claim 1, wherein the input receiver circuit comprises a capacitance.11. The apparatus of claim 10, wherein the capacitance is programmable.12. An apparatus comprising:an input circuit comprising:a first input receiver circuit configured to:receive a first input signal from a first input signal line;receive a reference signal from a reference signal line; andgenerate a first output signal;a second input receiver circuit configured to:receive a second input signal from a second input signal line;receive the reference signal from the reference signal line; andgenerate a second output signal;wherein the first input receiver circuit is further configured to receive the second input signal from the second input signal line and generate a mitigation signal based, at least in part, on the second input signal, wherein the first input signal includes at least a portion of the second input signal and the mitigation signal is configured to cancel at least a portion of the second input signal from the first input signal.13. The apparatus of claim 12, wherein the first input receiver circuit comprises a differential pair circuit configured to receive the reference signal on a reference side and receive the first input signal on an input side.14. The apparatus of claim 13, wherein the differential pair circuit is configured to provide the first output signal.15. The apparatus of claim 12, wherein the second input receiver circuit is further configured to receive the first input signal from the first input signal line and generate a second mitigation signal based, at least in part, on the first input signal, wherein the second input signal includes at least a portion of the first input signal and the second mitigation signal is configured to cancel at least a portion of the first input signal from the second input signal.16. A method, comprising:receiving, at an input receiver circuit, a first input signal from a first signal line;receiving a second input signal from a second signal line; andgenerating a mitigation signal, based at least in part, on the second input signal, wherein the first input signal includes at least a portion of the second data signal and the mitigation signal is configured to cancel at least a portion of the second data signal from the first data signal, wherein the mitigation signal is further based at least in part, on a third input signal, wherein the first input signal includes at least a portion of the third input signal and the mitigation signal is configured to cancel at least a portion of the third input signal from the first input signal.17. The method of claim 16, further comprising generating a second mitigation signal, based at least in part, on the second input signal and configured to cancel at least a portion of the second data signal from the first data signal.18. The method of claim 16, further comprising providing the mitigation signal for a period of time equal to a recovery time of the first input signal on the first input signal line.
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