The input circuit 300 includes input receiver circuits 310 that receive respective IN signals from the external terminals. Each of the input receivers 310 is caused by the CLK_t and CLK_c clocks to capture the respective IN signal. The input receivers 310 further receive a reference voltage VREF. The input receivers 310 compare a voltage of the respective IN signal to the VREF signal to determine a logic level of the respective IN signal and provide a respective output signal OUT having a voltage corresponding to a logic level that is based on the comparison. For example, an input signal having a voltage that is greater than the VREF voltage when captured by an input receiver is determined as a 1 logic level, and conversely, an input signal having a voltage that is less than the VREF voltage when captured by the input receiver is determined as a 0 logic level. In some examples, the input receiver 310 may include a differential pair circuit (not shown in FIG. 3), where one side receives the respective IN signal as an input and the other side receives the VREF as an input. The output of the differential pair may be used by the input receiver 310 to generate the respective output signal OUT. In some examples, the output of the differential pair may be a differential signal. The resulting respective output signals OUT provided by the input receivers have voltages that correspond to logic levels that are based on the logic levels of the respective input signals. The OUT signals may be provided to internal circuits for further operations, for example, other circuits included in the input/output circuit and/or read amplifiers, such as read amplifiers 255.