Another node of transistor 802 and another node of transistor 806 may be coupled to a bias current generator 810, which may be coupled to a common voltage-VSS in the example shown in FIG. 8. Current may flow from the load device 801 through the transistors 802 and 806 to the bias current generator 810. The gate of transistor 802 may receive an input signal from a signal line CH1 at an input 804. In some embodiments, the input signal may be a data signal received via a DQ signal line. A gate of transistor 806 may receive a reference voltage VREF at an input 808. In some embodiments, VREF may be provided by a voltage generator, such as voltage generator 270.