FIG. 10 is a circuit diagram of at least a portion of an input receiver circuit according to an embodiment of the present disclosure. In some embodiments, the input receiver circuit 1000 may be included in input receiver circuit 310. In some embodiments, the input receiver circuit 1000 may be used to implement input receiver circuit 500. The input receiver circuit 1000 may include a differential pair circuit 1007 including transistor 1002 on an input side and transistor 1006 on a reference side. A node of transistor 1002 and a node of transistor 1006 may be coupled to a load device 1001 of the input receiver circuit 1000. The load device 1001 may include one or more resistors, latches, transistors, and/or other devices. The load device 701 may provide an output signal OUT. In some examples, the output signal OUT may have a voltage level indicating a logic level, similar to the output signals OUT0-OUTn shown in FIG. 3. In other examples, the output signal OUT may be provided to other components of the input receiver circuit 1000 not shown that generate an output signal indicative of a logic level.
