FIG. 4 is an exemplary diagram depicting the assembly and fabrication process for making a wafer-scale clock chip, in various embodiments. The process begins by predefining metal layers on the two halves of the glass sandwich, machining the inner surfaces, and fusion bonding the wafers together (step 1). Separately, a silicon-on-insulator stack is formed with a device layer (e.g., a 200-μm layer) and a pre-fabricated handle with TSVs and RDLs (step 2). Si optical elements are etched into the device layer and release holes are etched into the surrounding area (step 3). Those release holes allow for releasing the Si surrounding the optical elements by removing the oxide layer using wet etching (step 4). The sides of the Si optical elements are then metalized, to increase reflectivity, using a shadow mask to avoid TSV and bond surfaces (step 5). Similarly, an evaporable getter is evaporated on the Si handle wafer surface, in step 5. Next, the MEMS mirrors are wire-bonded to TSVs; and the VCSEL assembly, photodiodes, and graphite NEG are die-bonded to the RDL on the handle wafer (step 6). The clock chip is completed by wafer-level bonding the glass atom tube structure to the Si handle wafer using Au—Au bonding (step 7). Finally, the photo-diode is attached to the top of the clock chip, and the Helmholtz coils are wire-bonded (step 8). All references in this paragraph to specific dimensions and materials are for purposes of illustrating this drawing only, and should be understood in the context of the entire specification.