Although a same one of the connection circuit board FPCB is shown connected to each of a plurality of pad areas PDA of the display panel DP, the invention is not limited thereto. In an embodiment, for example, two different types of connection circuit boards may be respectively connected to the pad areas PDA.

FIG. 2 is a top plan view illustrating an embodiment of a planar arrangement relationship between panel signal lines GL1 to GLn, DL1 to DLm, PL-G and PL-D and pixels PX11 to PXnm. The panel signal lines GL1 to GLn, DL1 to DLm, PL-G and PL-D may include a plurality of gate lines GL1 to GLn, a plurality of data lines DL1 to DLm, and auxiliary signal lines PL-G and PL-D.

The plurality of gate lines GL1 to GLn are arranged spaced apart from each other along the second direction DR2 while extending along the first direction DR1, and the plurality of data lines DL1 to DLm cross the plurality of gate lines GL1 to GLn in an insulating manner. The plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm are disposed to overlap or correspond to the display area DA. The auxiliary signal lines PL-G and PL-D are disposed to overlap or correspond to the non-display area NDA and are connected to the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm.

A gate auxiliary signal line PL-G is provided in plural including gate auxiliary signal lines PL-G connected to the plurality of gate lines GL1 to GLn may be disposed in a same layer as and integrated with the plurality of gate lines GL1 to GLn. As being in a same layer, elements may be respective portions of a same material layer, without being limited thereto.