High density magnetoresistive random access memory device
地域：
Hsin-Chu
摘要
The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.
說明書
The present invention relates to the field of semiconductor technology, and in particular, to a high-density magnetoresistive random access memory (MRAM) device and a manufacturing method thereof.
In a high-density magnetoresistive random access memory (MRAM) layout, a dummy magnetic tunnel junction (MTJ) pattern is provided on the word line strap of the MRAM cell array area. When forming the second via (V2) layer, different dielectric film structures need to be etched in the MRAM cell array area and logic area, respectively. Vias with negative slope profiles may be formed, resulting in poor step coverage in the subsequent Ta/TaN barrier layer and copper seed layer deposition processes. In some cases, undesired Cu void defects are formed.
It is one object of the present invention to provide an improved magnetoresistive random access memory device and a manufacturing method thereof to solve the above-mentioned deficiencies or shortcomings of the prior art.
權(quán)利要求
What is claimed is:1. A high-density magnetoresistive random access memory (MRAM) device, comprising:a substrate having a MRAM cell array area and a logic area; a first interlayer dielectric (ILD) layer disposed on the substrate within the MRAM cell array area and the logic area; a first metal pad and a second metal pad disposed in the first ILD layer within the MRAM cell array area and the logic area, respectively; a capping layer covering the first metal pad, the second metal pad, and the first ILD layer within the MRAM cell array area and the logic area; a second interlayer dielectric (ILD) layer covering the capping layer within the MRAM cell array area and the logic area, wherein the second ILD has a thickness in the MRAM cell array area greater than a thickness in the logic area, wherein the first thickness is greater than the second thickness, and wherein a composition of the second ILD layer in the logic area is different from a composition of the second ILD layer in the MRAM cell array area; a magnetic tunnel junction (MTJ) structure disposed on the second ILD layer within the MRAM cell array area; a protective layer conformally covering the MTJ structure and the second ILD layer within the MRAM cell array area; a third interlayer dielectric (ILD) layer covering the protective layer within the MRAM cell array area; and a fourth interlayer dielectric (ILD) layer covering the third ILD layer within the MRAM cell array area and the second ILD layer within the logic area. 2. The high-density MRAM device according to claim 1 , wherein the MTJ structure is a dummy MTJ structure. 3. The high-density MRAM device according to claim 2 further comprising:a local interconnect structure disposed on the dummy MTJ structure, wherein the local interconnect structure comprises a metal layer on the MTJ structure and a via layer electrically connecting the metal layer to the first metal pad. 4. The high-density MRAM device according to claim 3 , wherein the dummy MTJ structure comprises a top electrode and bottom electrode, wherein the top electrode is in direct contact with the metal layer, and the bottom electrode is not directly connected with the first metal pad. 5. The high-density MRAM device according to claim 1 further comprising:an interconnect structure electrically connected to the second metal pad, wherein the interconnect structure penetrates through the fourth ILD layer, the second ILD layer, and the capping layer. 6. The high-density MRAM device according to claim 1 , wherein the first metal pad is a word line strap. 7. The high-density MRAM device according to claim 1 , wherein the first ILD layer and the fourth ILD layer are ultra-low dielectric constant (ULK) layers. 8. The high-density MRAM device according to claim 1 , wherein the second ILD layer and the third ILD layer are silicon oxide layers. 9. The high-density MRAM device according to claim 1 , wherein the second ILD layer in the logic area has a nitrogen doping concentration that is higher than that of the second ILD layer in the MRAM cell array area. 10. The high-density MRAM device according to claim 1 , wherein the second ILD layer in the logic area has a gradient nitrogen doping concentration across its entire thickness. 11. The high-density MRAM device according to claim 1 , wherein the second ILD layer in the logic area has a uniform nitrogen doping concentration across its entire thickness. 12. The high-density MRAM device according to claim 1 , wherein the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer. 13. The high-density MRAM device according to claim 1 , wherein the protective layer comprises a silicon nitride layer. 14. A method for fabricating a high-density magnetoresistive random access memory (MRAM) device, comprising:providing a substrate having a MRAM cell array area and a logic area; forming a first interlayer dielectric (ILD) layer on the substrate within the MRAM cell array area and the logic area; forming a first metal pad and a second metal pad in the first ILD layer within the MRAM cell array area and the logic area, respectively; forming a capping layer covering the first metal pad, the second metal pad, and the first ILD layer within the MRAM cell array area and the logic area; forming a second interlayer dielectric (ILD) layer covering the capping layer within the MRAM cell array area and the logic area; forming a magnetic tunnel junction (MTJ) structure on the second ILD layer within the MRAM cell array area; forming a protective layer conformally covering the MTJ structure and the second ILD layer; forming a third interlayer dielectric (ILD) layer covering the protective layer; etching the third ILD layer, the protective layer, and the second ILD layer within the logic area; doping the second ILD layer within the logic area with dopants containing nitrogen; and forming a fourth interlayer dielectric (ILD) layer covering the third ILD layer within the MRAM cell array area and the second ILD layer within the logic area. 15. The method according to claim 14 , wherein the MTJ structure is a dummy MTJ structure. 16. The method according to claim 15 further comprising:forming a local interconnect structure on the dummy MTJ structure, wherein the local interconnect structure comprises a metal layer on the MTJ structure and a via layer electrically connecting the metal layer to the first metal pad. 17. The method according to claim 16 , wherein the dummy MTJ structure comprises a top electrode and bottom electrode, wherein the top electrode is in direct contact with the metal layer, and the bottom electrode is not directly connected with the first metal pad. 18. The method according to claim 14 further comprising:forming an interconnect structure electrically connected to the second metal pad, wherein the interconnect structure penetrates through the fourth ILD layer, the second ILD layer, and the capping layer. 19. The method according to claim 14 , wherein the first ILD layer and the fourth ILD layer are ultra-low dielectric constant (ULK) layers. 20. The method according to claim 14 , wherein the second ILD layer and the third ILD layer are silicon oxide layers. 21. The method according to claim 14 , wherein the second ILD layer in the logic area has a nitrogen doping concentration that is higher than that of the second ILD layer in the MRAM cell array area. 22. The method according to claim 14 , wherein the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer. 23. The method according to claim 14 , wherein the protective layer comprises a silicon nitride layer.
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