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Method for forming semiconductor structure

專利號(hào)
US12161057B2
公開日期
2024-12-03
申請(qǐng)人
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.(TW Hsinchu)
發(fā)明人
Hsing-Lien Lin; Fu-Ting Sung; Ching Ju Yang; Chii-Ming Wu
IPC分類
H10N70/00; G11C13/00; H10B63/00; H10N70/20
技術(shù)領(lǐng)域
layer,nucleation,conductive,in,dielectric,pillar,sidewall,memory,structure,210t
地域: Hsinchu

摘要

A method for forming a semiconductor memory structure include forming a pillar structure. The pillar structure includes a first conductive layer, a second conductive layer and a data storage material layer between the first and second conducive layers. A sidewall of the first conductive layer, a sidewall of the data storage layer and a sidewall of the second conductive layer are exposed. An oxygen-containing plasma treatment is performed on the pillar structure to form hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer. An encapsulation layer is formed over the pillar structure and the dielectric layer. The encapsulation layer is in contact with the hydrophilic surfaces of the sidewall of the first conductive layer, the sidewall of the data storage layer and the sidewall of the second conductive layer.

說明書

In some embodiments, a trench (not shown) may be formed in the dielectric layer 154, a barrier layer (not shown) may be formed to line a bottom and sidewalls of the trench, and a conductive layer (not shown) may be formed on the barrier layer and to fill the trench. The conductive layer can include materials similar to those used to form the metal layers Mn; therefore, descriptions of such details are omitted for brevity. It should be understood that to mitigate metal diffusion, which may adversely affect electrical isolation of the surrounding IMD layers, the barrier layer may be required. Therefore, when the conductive layer includes Cu, the barrier layer can include conductive materials that form a Cu diffusion barrier. In some embodiments, a planarization may be performed to remove a superfluous conductive layer and a superfluous barrier layer. Accordingly, a via, such as a top via TEVA, can be obtained. The top via TEVA is coupled to the second conductive layer 144, as shown in FIG. 11.

權(quán)利要求

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