A semiconductor memory cell, such as a phase change memory (PCM) cell, may include a data-storage element between a top electrode and a bottom electrode. When forming the memory cell, a first conductive layer, a data storage layer, and a second conductive layer may be sequentially formed, and a patterned hard mask is formed over the stacked layers. The bottom conductive layer, the data storage layer and the top conductive layer may be etched through the patterned hard mask to form a plurality of pillars respectively including the patterned first conductive layer serving as the bottom electrode, the patterned data storage layer serving as the data-storage element, and the patterned second conductive layer serving as the top electrode. In some comparative approaches, an encapsulation layer may be formed to cover sidewalls of each cell pillar in order to protect the sidewalls of the pillars in subsequent manufacturing operations.

In some embodiments, a measure of how well a layer is formed is expressed by a ratio of a minimum thickness of the layer as it crosses a step, to a thickness of the layer on flat regions. This layer property is referred to as the “step coverage” of the layer. It is found that an aspect ratio, which is defined as a height to a width of a feature, may affect the step coverage. For example, the greater the aspect ratio of the feature is, the more difficult it is to have a uniform step coverage. In some comparative approaches, an aspect ratio of the cell pillars may be greater than approximately 20. It is found that the encapsulation layer suffers from the step coverage issue.