If the same current value IC is forced to flow through the MTJ cell by the current source 30, it is found that the cell voltage V1 in the case of FIG. 3A (or FIG. 3C) is larger than the cell voltage V2 in the case of FIG. 3B (or FIG. 3D), because the resistance of an opposite-oriented MTJ cell shown in FIG. 3A (or FIG. 3C) is greater than the resistance of a same-oriented MTJ cell shown in FIG. 3B (or FIG. 3D). Binary logic data (“0” and “1”) can be stored in a MTJ cell and retrieved based on the cell orientation and resulting resistance. Further, since the stored data does not require a storage energy source, the cell is non-volatile.
FIG. 4A shows a schematic circuit diagram of an MTJ MRAM array 50. Each memory cell includes a MTJ cell Mc and a transistor Tr, such as a MOS FET. The gate of the transistor Tr is coupled to one of word lines WL1 . . . WLm and a drain (or a source) of the transistor Tr is coupled to one end of the MTJ cell Mc, and another end of the MTJ cell is coupled to one of bit lines BLn, BLn+1 and BLn+2. Further, in some embodiments, signal lines (not shown) for programming are provided adjacent to the MTJ cells.
