As shown in FIG. 5, a first insulating layer as an etch stop layer 220 is formed on the first ILD layer 210. In some embodiments, the first insulating layer 220 includes a material different from the first ILD layer 210 and includes silicon carbide, silicon nitride, aluminum oxide or any other suitable material. The thickness of the first insulating layer 220 is in a range from about 10 nm to about 25 nm in some embodiments.

A second ILD layer 225 is formed over the first insulating layer 220. The second ILD layer includes one or more dielectric layers, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. In some embodiments, the material for the first ILD layer 210 and the material for the second ILD layer 225 are the same. In other embodiments, different dielectric materials are used for the first ILD layer 210 and the second ILD layer 225.

A via contact 219 is formed in contact with the lower metal wiring 215 and passing through the second ILD layer 225 and the first etch stop layer 220 in some embodiments. In some embodiments, the via contact 219 includes a liner layer 215 and a body layer 217. The liner layer 215 includes one or more layers of Ti, TiN, Ta or TaN, or other suitable material, and the body layer 217 includes one or more layers of W, Cu, Al, Mo, Co, Pt, Ni, and/or an alloy thereof or other suitable material, in some embodiments.