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Magnetic random access memory and manufacturing method thereof

專利號(hào)
US12178051B2
公開日期
2024-12-24
申請人
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.(TW Hsinchu)
發(fā)明人
Hui-Hsien Wei; Chung-Te Lin; Han-Ting Tsai; Tai-Yen Peng; Yu-Teng Dai; Chien-Min Lee; Sheng-Chih Lai; Wei-Chih Wen
IPC分類
H10B61/00; B82Y25/00; G11C11/16; H01F41/30; H10N50/01; H10N50/10; H10N50/80; H10N50/85
技術(shù)領(lǐng)域
layer,insulating,mtj,mram,ild,cover,in,electrode,nm,dielectric
地域: Hsinchu

摘要

In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

說明書

Further, a second insulating cover layer 280 is formed over the first insulating cover layer 227. The second insulating cover layer 280 includes one or more layers of insulating material different from the first insulating cover layer 227. In some embodiments, an aluminum-based insulating material is used. In certain embodiments, the aluminum-based insulating material includes aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum carbide and/or aluminum oxycarbide. In some embodiments, the concentrations of Al, O, C and/or N in the thickness direction are not uniform. In certain embodiments, the concentration of Al gradually decreases from the bottom to the top of the second insulating cover layer 280, while the concentrations of O, C and/or N gradually increase from the bottom to the top of the second insulating cover layer 280. The thickness T2 of the second insulating cover layer 270 is smaller than the thickness T1 of the first insulating cover layer in some embodiments. The thickness T2 is in a range from about 1 nm to about 10 nm in some embodiments, and is in a range from about 3 nm to about 5 nm in other embodiments.

Further a third ILD layer 230 is disposed in spaces between the MRAM cell structures. The third ILD layer 230 includes one or more dielectric layers, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. In some embodiments, the material for the first ILD layer 210, the material for the second ILD layer 225 and the material for the third ILD layer 230 are the same. In other embodiments, at least two of them are made of different dielectric materials.

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