As shown in FIG. 6A, lower metal wirings 213 are formed in the first ILD layer 210 over the substrate 201. In some embodiments, via contacts 207 are provided under the lower metal wirings 213. Then, as shown in FIG. 6B, a first insulating layer as an etch stop layer 220 is formed over the structure of FIG. 6A, and a second ILD layer 225 is formed over the first insulating layer 220. Further, as shown in FIG. 6B, via contact openings 222 are formed to expose the upper surface of the lower metal wirings 213, by using one or more lithography and etching operations. Subsequently, via contact 219 including layers 215 and 217 are formed, as shown in FIG. 6C. One or more film forming operations, such as CVD, PVD including sputtering, ALD, electro-chemical plating and/or electro-plating, are performed, and a planarization operation, such as CMP, is performed to fabricate the via contacts 219.

Then, as shown in FIG. 7A, a first conductive layer 254A for the bottom electrode 254, a stacked layer 255A for the MTJ film stack 255 and a second conductive layer 256A for the top electrode 256 are sequentially formed. In some embodiments, a layer 300 for a hard mask is further formed on the second conductive layer 256A.