FIGS. 13A and 13B show various stages of a sequential manufacturing process of the semiconductor device including an MRAM according to another embodiment of the present disclosure. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described with FIGS. 1A-12B may be employed in the following embodiments, and detailed explanation thereof may be omitted.
Similar to FIGS. 12A and 12B, in the embodiments shown by FIGS. 13A and 13B, the upper surface of the top electrode 256 is not flush with at least one of the upper surfaces of the first insulating cover layer 227 and the second insulating cover layer 280.