In some embodiments, the upper surface of the top electrode 256 is higher than the upper surface of the first insulating cover layer 227 and lower than the upper surface of the second insulating cover layer 280. In other words, a vertical level of an upper surface of the top electrode 256 is higher than a vertical level of an upper surface of the first insulating cover layer 227 and lower than a vertical level of an upper surface of the second insulating cover layer 280, measured from the substrate. A difference D2 between the upper surface of the top electrode 256 and the upper surface of the first insulating cover layer 227 is more than 0 nm and less than about 20 nm in some embodiments, and is more than 0 nm and less than about 10 nm in other embodiments. A difference D5 between the upper surface of the top electrode 256 and the upper surface of the second insulating cover layer 280 is more than 0 nm and less than about 15 nm in some embodiments, and is more than 0 nm and less than about 5 nm in other embodiments. Further, in some embodiments, a difference D4 between the upper surface of the first insulating cover layer 227 and the interface between the MTJ film stack 255 and the top electrode 256 is more than 10 nm in some embodiments, and is more than 20 nm in other embodiments, where D2+D4 is equal to the thickness of the top electrode 256. In other words, sidewalls of the MTJ film stack 255 is fully covered by the first insulating cover layer 227.