For example, the manufacturing method of the display panel shown in FIG. 1A to FIG. 3B includes: sequentially forming the following structures on the base substrate 11: a switching element 19 (for example, the first source/drain electrode layer 1710 where the source electrode 193 and the drain electrode 194 of the switching element 19 are located also includes the first conductive layer 171), a passivation insulating layer PVX, a first planarization insulating layer PLN1, a second source/drain electrode layer 174 including a connection portion 194A (for example, the second source/drain electrode layer 1721 also includes a first sub-conductive layer 172A), a second planarization insulating layer PLN2, a first electrode layer 121 (for example, the electrode layer 1722 where first electrode layer 121 is located also includes a second sub-conductive layer 172B), a pixel defining layer PDL, a light emitting layer 123, a second electrode layer 122 (for example, the electrode layer 1723 where the second electrode layer 122 is located also includes a third sub-conductive layer 172C), an encapsulation layer EPL (which includes, for example, a first inorganic encapsulation layer EPL1, a first organic encapsulation layer EPL3, and a second inorganic encapsulation layer EPL2, in which the first organic encapsulation layer EPL3 is not overlapped with the cover plate alignment marks 14), and a touch structure 15 (which includes, for example, a buffer layer BFL, a conductive layer 15B, a second intermediate insulating layer IIL2, a conductive layer 15A, and a protective layer PL, the layer where the conductive layer 15B and/or the conductive layer 15A is located also includes the plurality of cover plate alignment marks 14).
