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Electronic device

專利號
US12178090B2
公開日期
2024-12-24
申請人
LG Display Co., Ltd.(KR Seoul)
發(fā)明人
SeHee Park; InTak Cho; PilSang Yun
IPC分類
H10K59/131; G09G3/3291; H10K59/124
技術(shù)領(lǐng)域
layer,insulating,transistor,electrode,gate,active,may,disposed,first,region
地域: Seoul

摘要

Provided is an electronic device. The electronic device includes at least one first transistor to which a data voltage is applied. The first transistor includes a first conductive layer disposed on a substrate and a first active layer, which is disposed on the first conductive layer, has one end and the other end which are made conductive, and includes a first channel region disposed between the one end and the other end. A second conductive layer overlapping the first conductive layer with a first insulating layer interposed between the second conductive layer and the first conductive layer is included in a storage capacitor in a panel, and the storage capacitor is disposed under the first channel region of the first active layer. In this way, an ultra-high definition panel is fabricated.

說明書

Also, as shown in FIG. 35, the third conductive layer 480 may be disposed in the contact hole 490, which exposes a part of the upper surface of the first conductive layer 450, and may be in contact with the first conductive layer 450.

In this case, the first conductive layer 450 may be electrically connected to a ground line.

Meanwhile, FIG. 12 and FIGS. 27 to 35 show a structure in which the third conductive layer 480 is electrically connected to the first conductive layer 450 through the contact hole 490, which exposes a part of the upper surface of the first conductive layer 450, but the present disclosure is not limited thereto.

For example, the second conductive layer 451 (integrated with the fourth active layer 430) may extend under the contact hole 490, and the third conductive layer 480 may be electrically connected to the second conductive layer 451 through the contact hole 490. In this case, the third conductive layer 480 may serve as the gate electrode of the the third transistor T3 together with the second conductive layer 451.

Subsequently, as shown in FIG. 36, the fourth insulating layer 506 may be formed on the substrate 400 on which the third conductive layer 480 is formed.

In a panel including transistors having the above-described structure, the area of subpixels SP may be reduced, and thus it is possible to achieve high resolution.

權(quán)利要求

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