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Electronic device

專利號
US12178090B2
公開日期
2024-12-24
申請人
LG Display Co., Ltd.(KR Seoul)
發(fā)明人
SeHee Park; InTak Cho; PilSang Yun
IPC分類
H10K59/131; G09G3/3291; H10K59/124
技術領域
layer,insulating,transistor,electrode,gate,active,may,disposed,first,region
地域: Seoul

摘要

Provided is an electronic device. The electronic device includes at least one first transistor to which a data voltage is applied. The first transistor includes a first conductive layer disposed on a substrate and a first active layer, which is disposed on the first conductive layer, has one end and the other end which are made conductive, and includes a first channel region disposed between the one end and the other end. A second conductive layer overlapping the first conductive layer with a first insulating layer interposed between the second conductive layer and the first conductive layer is included in a storage capacitor in a panel, and the storage capacitor is disposed under the first channel region of the first active layer. In this way, an ultra-high definition panel is fabricated.

說明書

FIG. 5 is a diagram schematically illustrating a gate driving circuit GDC disposed in the panel PNL according to embodiments of the present disclosure.

Referring to FIG. 5, each gate driving circuit GDC may include a pull-up transistor Tup, a pull-down transistor Tdown, a control switch circuit CSC, and the like.

The control switch circuit CSC is a circuit which controls the voltage of a node Q corresponding to the gate node of the pull-up transistor Tup and the voltage of a node QB corresponding to the gate node of the pull-down transistor Tdown and may include several switches (transistors).

The pull-up transistor Tup supplies a gate signal Vgate corresponding to a first level voltage (e.g., a high level voltage VGH) to a gate line GL through a gate signal output node Nout. The pull-down transistor Tdown supplies the gate signal Vgate corresponding to a second level voltage (e.g., a low level voltage VGL) to the gate line GL through the gate signal output node Nout. The pull-up transistor Tup and the pull-down transistor Tdown may be turned on at different timings.

The pull-up transistor Tup is electrically connected between a clock signal application node Nclk to which the clock signal CLK is applied and the gate signal output node Nout electrically connected to the gate line GL and is turned on or off by the voltage of the node Q.

The gate node of the pull-up transistor Tup is electrically connected to the node Q. The drain node or the source node of the pull-up transistor Tup is electrically connected to the clock signal application node Nclk. The source node or the drain node of the pull-up transistor is electrically connected to the gate signal output node Nout to which the gate signal Vgate is output.

權利要求

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