Electronic device
摘要
說明書
In the case of a high-resolution panel, the area of subpixels SP is reduced, and widths W of a plurality of holes disposed in the subpixels SP may also be reduced accordingly.
Since the current characteristic of transistors may be degraded in the high-resolution panel due to the reduction in the widths W of holes, channels may be formed with short lengths to ensure the current characteristic of the transistors.
According to the embodiment of the present disclosure, the length of the first channel region CHA1 may be adjusted through the thickness of the first to third insulating layers 201 to 203.
In other words, according to the embodiment of the present disclosure, the length of the first channel region CHA1 may be shortened by forming the first to third insulating layers 201 to 203 to be thin.
Also, the length of the first channel region CHA1 disposed on the first to third insulating layers 201 to 203 in the first hole H1 may be adjusted by adjusting an angle Z between the substrate 100 and the first to third insulating layers 201 to 203. In this way, the length of the first channel region CHA1 may be adjusted to be applicable to a high-resolution panel.
Although
A structure of a first active layer according to another embodiment of the present disclosure will be described below with reference to
