Electronic device
摘要
說明書
In other words, in the first transistor T1 according to the embodiment of the present disclosure, the length of the fourth channel region CHA4 in the fourth active layer 430 is not determined through an exposure process or the like and may be adjusted only by adjusting the thickness of the first and second insulating layers 401 and 402.
The first transistor T1 including the fourth active layer 430 having the above-described structure may occupy a reduced area in the panel and thus can facilitate fabrication of a high-resolution panel.
As shown in
Also, the third gate insulating layer 531 may be disposed under the first and second gate lines 460 and 461 so that the first and second gate lines 460 and 461 may overlap the third gate insulating layer 531. Also, the third gate insulating layer 531 may be disposed under the first gate electrode 462 and a second gate electrode 463 branching from the first gate line 460 so that the the first gate electrode 462 and the second gate electrode 463 may overlap the third gate insulating layer 531.
Specifically, the third gate insulating layer 531 may overlap the first to third regions 431 to 433 of the fourth active layer 430. In another aspect, the third gate insulating layer 531 may be disposed to expose the fourth region 434 of the fourth active layer 430.
