Display apparatus
摘要
說明書
The data timing control signal DDC may include a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, or the like. The source start pulse SSP controls a starting time point of data sampling by the data driver 130 and is provided to the data driver 130 at a starting time point of the scanning period. The source sampling clock SSC may include a clock signal for controlling a sampling operation of data within the data driver 130 based on a rising or falling edge. The source output enable signal SOE controls outputting by the data driver 130. The source start pulse SSP provided to the data driver 130 may be omitted according to data transmission schemes.
The gate driver 120 sequentially generates the first scan signals GW_1 to GW_m, the second scan signals GI_1 to GI_m, and the third scan signals GB_1 to GB_m in response to the gate timing control signal GDC received from the timing controller 140 using the first and second gate voltages VGH and VGL provided from the voltage generator 150.
The data driver 130 samples and latches image data DATA supplied from the timing controller 140 in response to the data timing control signal DDC received from the timing controller 140, and converts the image data DATA into data of a parallel data system. When the data driver 130 converts the image data DATA into data of the parallel data system, the image data DATA is converted into a gamma reference voltage and converted into an analog data voltage. The data driver 130 provides the data voltages Dm_1 to Dm_n to the pixels PX through the data lines DL_1 to DL_n. The pixels PX receives the data voltages Dm_1 to Dm_n in response to the first scan signals GW_1 to GW_m.
