Display panel
地域：
Hubei
摘要
The present application provides a display panel. The display panel includes a plurality of data lines, a plurality of constant voltage traces, and a plurality of drive traces located in a display area. The display panel further includes a first metal layer, a second metal layer, and a shield layer between the first metal layer and the second metal layer, wherein the first metal layer includes a gate trace, the shield layer includes a plurality of shield traces, and the second metal layer includes the drive trace. An overlap region of the drive trace and the gate trace on the shield layer overlaps with the shield trace.
說(shuō)明書(shū)
This application claims priority to Chinese Patent Application No. 202111494060.X, filed with the Chinese Patent Office on Dec. 8, 2021, and entitled “DISPLAY PANEL”, the entire content of which is incorporated herein by reference.
The present application relates to a field of display technology, and in particular to a display panel.
With the increasing proportion of the display area of the OLED (Organic Light-emitting Diode) display panel and the market demand for the irregular bezel, the wiring space at the edge of the display panel is challenged. The portion of the display panel that occupies a relatively large proportion of the edge space is a portion where the signal line from the drive chip enters the display area, and the line is generally fan-shaped, also referred to as a fan-out trace. In order to adapt to the present situation that the edges of the display panel gradually decrease, a design scheme is proposed in which the fan-out traces are arranged in the display area, and the design scheme gradually becomes a key technology for compressing the edges of the display panel. However, since the fan-out traces serve as a channel for the drive chip to transmit signals to the display area, the electrical signals present in the fan-out traces interfere with the signals in the gate traces connected to the drive transistors in the display area, resulting in abnormal display of the display panel.
The present display panel has a technical problem that the fan-out traces located in the display area interfere with the signal transmitted by the gate traces.
權(quán)利要求
What is claimed is:1. A display panel, comprising a display area and a non-display area adjacent to the display area, wherein the display panel comprises:a substrate; a drive circuit layer disposed on the substrate, wherein the drive circuit layer comprises: a plurality of data lines and a plurality of constant voltage traces located in the display area, and a plurality of drive traces located at least partially in the display area and electrically connected to the data lines and a drive chip; wherein the drive circuit layer further comprises a first metal layer, a second metal layer, and a shield layer between the first metal layer and the second metal layer, the first metal layer comprises a plurality of gate traces, the shield layer comprises a plurality of shield traces electrically connected to the constant voltage traces, the second metal layer comprises the drive traces, and an overlap region of at least a portion of an orthographic projection of the drive trace on the shield layer and at least a portion of orthographic projection of the gate trace on the shield layer overlaps with the shield trace; wherein the display panel further comprises a fourth metal layer located on a side of the second metal layer away from the shield layer, the fourth metal layer comprises a plurality of shelter traces located in the display area; the second metal layer comprises a plurality of virtual traces electrically insulated from the drive traces and the drive chip, the display panel comprises a plurality of sub-pixels, the virtual traces in two adjacent sub-pixels are disconnected from each other, and an orthographic projection of the shelter trace on the second metal layer covers at least a portion of a disconnection region of the virtual traces in two adjacent sub-pixels. 2. The display panel according to claim 1 , wherein an orthographic projection of at least a portion of the drive trace on the shield layer overlaps with the shield trace, and an orthographic projection of at least a portion of the gate trace on the shield layer overlaps with the shield trace. 3. The display panel according to claim 2 , wherein the orthographic projection of the drive trace on the shield layer overlaps with the shield trace. 4. The display panel according to claim 1 , wherein the display panel comprises a first sub-pixel and a second sub-pixel arranged in a second direction, a number of the drive traces included in the first sub-pixel extending in the first direction is greater than a number of the drive traces included in the second sub-pixel extending in the first direction, and the shield trace is disposed in the first sub-pixel. 5. The display panel according to claim 1 , wherein the display panel comprises a first sub-pixel and a second sub-pixel arranged in a second direction, a number of the drive traces included in the first sub-pixel extending in the first direction is greater than a number of the drive traces included in the second sub-pixel extending in the first direction, and the shield trace is disposed in the first sub-pixel and the second sub-pixel. 6. The display panel according to claim 3 , wherein the drive circuit layer further comprises a third metal layer disposed between the first metal layer and the shield layer, the third metal layer comprises the data line, the constant voltage trace, and a gate connection line electrically connected to the gate trace, the shield trace covers at least an overlap region of an orthographic projection of the data line, the constant voltage trace, and the gate connection line on the shield layer and the orthographic projection of the drive trace on the shield layer. 7. The display panel according to claim 1 , wherein a connection point of the drive trace and the data line is located in the display area. 8. The display panel according to claim 7 , wherein a number of connection points of each drive trace and the data line is one or more. 9. The display panel according to claim 7 , wherein an end of the drive trace terminates at the connection point of the drive trace and the data line. 10. The display panel according to claim 1 , whereinthe display area comprises a first display area provided with the drive trace and a second display area adjacent to the first display area; a distribution shape of the shelter traces in the first display area is the same as a distribution shape of the shelter traces in the second display area, and an orthographic projection of the drive trace in the display area on the fourth metal layer overlaps with the shelter trace. 11. The display panel according to claim 10 , wherein a distribution shape of a layout of the shelter traces in the fourth metal layer is the same as a distribution shape of the drive traces in the second metal layer. 12. The display panel according to claim 10 , wherein the shelter trace is closer to a light-emitting side of the display panel than the drive trace. 13. The display panel according to claim 1 , wherein the plurality of the virtual traces comprise a first virtual trace extending in a first direction and a second virtual trace extending in a second direction;an orthographic projection of the shelter trace on the second metal layer covers a disconnection region of the first virtual traces in two adjacent sub-pixels. 14. The display panel according to claim 13 , wherein the orthographic projection of the shelter trace on the second metal layer covers a disconnection region of the second virtual traces in two adjacent sub-pixels. 15. The display panel according to claim 1 , wherein an orthographic projection of the drive trace on the fourth metal layer overlaps with the shield trace, and an orthographic projection of the virtual trace on the fourth metal layer overlaps with the shield trace. 16. The display panel according to claim 1 , wherein the display area comprises a first display area provided with the drive trace, and a second display area adjacent to the first display area; a distribution shape of the shelter trace in the first display area is the same as a distribution shape of the shelter trace in the second display area. 17. The display panel according to claim 10 , wherein the shelter trace is electrically connected to the constant voltage trace. 18. The display panel according to claim 1 , wherein the shelter trace is electrically connected to the constant voltage trace. 19. A display panel, comprising a display area and a non-display area adjacent to the display area, wherein the display panel comprises:a substrate; a drive circuit layer disposed on the substrate, wherein the drive circuit layer comprises a plurality of data lines and a plurality of constant voltage traces located in the display area, and a plurality of drive traces located at least partially in the display area and electrically connected to the data lines and a drive chip; wherein the drive circuit layer further comprises a first metal layer, a second metal layer, and a shield layer between the first metal layer and the second metal layer, the first metal layer comprises a plurality of gate traces, the shield layer comprises a plurality of shield traces electrically connected to the constant voltage traces, the second metal layer comprises the drive traces; the display panel comprises a first sub-pixel and a second sub-pixel arranged in a second direction, a number of the drive traces included in the first sub-pixel extending in the first direction is greater than a number of the drive traces included in the second sub-pixel extending in the first direction, and the shield trace is disposed in the first sub-pixel, and an orthographic projection of the drive trace on the shield layer overlaps with the shield trace. 20. A display panel, comprising a display area and a non-display area adjacent to the display area, wherein the display panel comprises:a substrate; a drive circuit layer disposed on the substrate, wherein the drive circuit layer comprises: a plurality of data lines and a plurality of constant voltage traces located in the display area, and a plurality of drive traces located at least partially in the display area and electrically connected to the data lines and a drive chip; wherein the drive circuit layer further comprises a first metal layer, a second metal layer, and a shield layer between the first metal layer and the second metal layer, the first metal layer comprises a plurality of gate traces, the shield layer comprises a plurality of shield traces electrically connected to the constant voltage traces, the second metal layer comprises the drive traces, and an overlap region of at least a portion of an orthographic projection of the drive trace on the shield layer and at least a portion of orthographic projection of the gate trace on the shield layer overlaps with the shield trace; wherein the display panel comprises a first sub-pixel and a second sub-pixel arranged in a second direction, a number of the drive traces included in the first sub-pixel extending in the first direction is greater than a number of the drive traces included in the second sub-pixel extending in the first direction, and the shield trace is disposed in the first sub-pixel and the second sub-pixel.
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