Similarly, as illustrated in FIG. 6, on the second surface (the surface 30S2) of the semiconductor substrate 30, for example, n+ regions serving as the floating diffusions FD1 to FD3 are formed, and thereafter, a gate insulating layer 33 and a gate wiring layer 47 including respective gates of the transfer transistor Tr2, the transfer transistor Tr3, the selection transistor SEL, the amplifier transistor AMP, and the reset transistor RST are formed. Thus, the transfer transistor Tr2, the transfer transistor Tr3, the selection transistor SEL, the amplifier transistor AMP, and the reset transistor RST are formed. Further, the multilayer wiring 40 including the wiring layers 41 to 43 and the insulating layer 44 is formed on the second surface (the surface 30S2) of the semiconductor substrate 30. The wiring layers 41 to 43 include the first lower contact 45, the second lower contact 46, and the coupling section 41A.
As a base substrate of the semiconductor substrate 30, an SOI (Silicon on Insulator) substrate is used in which the semiconductor substrate 30, an embedded oxide film (not illustrated), and a retaining substrate (not illustrated) are stacked. The embedded oxide film and the retaining substrate are not illustrated in FIG. 6, but are joined to the first surface (the surface 30S1) of the semiconductor substrate 30. Annealing treatment is performed after ion implantation.
