The base portion 4 is provided below the first stacked body 1 and includes a substrate 40, a base insulating film 41, a base conductive film 42, and a base semiconductor portion 43. The substrate 40 has a first surface and a second surface that are substantially perpendicular to the Z direction, which is the stacking direction. The base insulating film 41 is provided on the first surface of the substrate 40. The base conductive film 42 is provided on the base insulating film 41. The base semiconductor portion 43 is provided on the base conductive film 42. The substrate 40 is configured with a semiconductor substrate, and may be, for example, a p-type silicon substrate. For example, an element division region 40i is provided on the surface region of the substrate 40. The element division region 40i is, for example, an insulating region containing silicon oxide, and an active area aa is partitioned on the surface region of the substrate 40. The source and drain regions of a transistor Tr are provided in the active area aa. The transistor Tr configures a peripheral circuit of the non-volatile memory. The base insulating film 41 contains, for example, a silicon oxide and insulates the transistor Tr. A wiring 41a is provided in the base insulating film 41. The wiring 41a is a wiring electrically connected to the transistor Tr. For example, a conductive metal such as tungsten is used for the base conductive film 42. For example, a semiconductor material such as n-type silicon is used for the base semiconductor portion 43. Undoped silicon may be used for a portion of the base semiconductor portion 43. The base conductive film 42 and the base semiconductor portion 43 integrally function as a common source line BSL of the memory cell array.