As illustrated in FIG. 1B, in a plan view seen from the Z direction, the first stacked body 1, the second stacked body 2, and the third stacked body 3 include a staircase portion 2s and a memory cell array 2m. In the staircase portion 2s, the memory cell array 2m is interposed between or surrounded by the staircase portion 2s. The slit ST is provided from the staircase portion 2s at one end of the stacked bodies 1 to 3 to the staircase portion 2s at the other end of the stacked body over the memory cell array 2m. The portion of the stacked bodies 1 to 3 interposed between the slits ST is called a block BLOCK. The block configures, for example, the smallest unit of data erasure. As described above, the block BLOCK is further partitioned in finer units by the first division insulating film 50. The on/off state of the drain-side select gate SGDO can be controlled in units (fingers) partitioned by the first division insulating film 50. The finger is a unit at the time of writing and reading data. By selecting the drain-side select gate SGDO corresponding to one finger in the block, the data of the memory cell corresponding to the finger can be read or written at a time. The layout of the memory cell array 2m and the staircase portion 2s is not limited thereto, and any layout may be designed.
