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Method for manufacturing a semiconductor storage device including a division film

專利號
US12185539B2
公開日期
2024-12-31
申請人
Kioxia Corporation（JP Tokyo）
發(fā)明人
Kazuharu Yamabe; Yoshiro Shimojo
IPC分類
H10B43/27
技術(shù)領(lǐng)域
columnar,film,insulating,sgdo,cl2a,cl2b,body,stacked,conductive,bodies
地域： Tokyo

摘要

In a method for manufacturing a memory, a first stacked body is formed by stacking a first insulating film and a first sacrificial film. A first columnar body including a first semiconductor portion extending in the first stacked body in the first direction and a charge trapping film provided on an outer peripheral surface of the first semiconductor portion is formed. A second columnar body provided in a second direction of the first columnar body and including a second semiconductor portion stretching in the first stacked body in the first direction and a charge trapping film on an outer peripheral surface of the second semiconductor portion is formed. A second insulating film is formed above the first stacked body. A third columnar body including a third semiconductor portion provided on both the first columnar body and the second columnar body and stretching in the second insulating film in the first direction and a first gate insulating film provided on an outer peripheral surface of the third semiconductor portion is formed. A first division insulating film extending in the first direction and a third direction intersecting the first direction and the second direction and dividing the third semiconductor portion of the third columnar body in the second direction is formed.

說明書

Also in the fourth embodiment, the four bit lines BL1 to BL4 are provided with respect to one active area Aa (a pair of the adjacent columnar bodies CL2). That is, the columnar body CL2 and the bit line BL are provided at a ratio of 1:2. On the other hand, the two active areas Aa adjacent in the stretching direction (Y direction) of the bit line BL are deviated by a half pitch in the X direction and share the two bit lines BL. Therefore, for example, the pair of columnar bodies CL2A and CL2B in FIG. 19A correspond to the four bit lines BL1 to BL4. The pair of columnar bodies CL2C and CL2D adjacent to the pair of columnar bodies CL2A and CL2B share only the bit lines BL3 and BL4 among the bit lines BL1 to BL4 together with the pair of columnar bodies CL2A and CL2B. Since the pair of columnar bodies CL2E and CL2F adjacent to the pair of columnar bodies CL2C and CL2D deviate by one pitch in the X direction with respect to the pair of columnar bodies CL2A and CL2B, the pair of columnar bodies CL2E and CL2F share the bit lines BL1 to BL4 together with the pair of columnar bodies CL2A and CL2B. As described above, in the fourth embodiment, the active areas Aa adjacent to each other in the Y direction share two bit lines. The active areas Aa intermittently adjacent in the Y direction share four bit lines BL.

The contacts VY1 to VY4 are provided on the contacts CH1 to CH4, respectively, and the contacts CH1 to CH4 are connected to the bit lines BL1, BL3, BL2, and BL4, respectively.

權(quán)利要求

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