Bi-directional buffer with circuit protection time synchronization
地域：
CA
CA Santa Clara
摘要
Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.
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Time synchronization involves synchronizing clocks such as those using time stamps between different devices. For example, IEEE 1588-2008 Precision Time Protocol (PTP) synchronizes time between different nodes on an Ethernet network. The IEEE 1588-2008 protocol depends on exchange of time-stamped frames between a device that uses a timing master clock and another device that uses a timing receiver clock. The IEEE 1588 standards describe a hierarchical primary-secondary architecture for clock distribution. Under this architecture, a time distribution system consists of one or more communication media (network segments), and one or more clocks. An ordinary clock is a device with a single network connection and is either the source of (primary or master) or destination for (secondary or slave) a synchronization reference. A boundary clock has multiple network connections and can accurately synchronize one network segment to another. A synchronization master is selected for each of the network segments in the system. The root timing reference is called the grandmaster. The grandmaster transmits synchronization information to the clocks residing on its network segment. The boundary clocks with a presence on that segment then relay accurate time to the other segments to which they are also connected.
A simplified PTP system frequently consists of ordinary clocks connected to a single network, and no boundary clocks are used. A grandmaster is elected and all other clocks synchronize directly to it. IEEE 1588-2008 introduces a clock associated with network equipment used to convey PTP messages. The transparent clock modifies PTP messages as they pass through the device. Timestamps in the messages are corrected for time spent traversing the network equipment.
權(quán)利要求
What is claimed is:1. An apparatus comprising:a circuitry to generate a timing signal by calibration of the timing signal and a received signal and based on a primary-secondary clock scheme, wherein the received signal comprises a 1 PPS signal, a 10 MHz signal, or other frequency clock signal; a receive circuitry path to transfer the received signal to the circuitry, wherein the receive circuitry path comprises an isolation circuit and second circuitry to receive different voltage level ranges of the received signal; a transmit circuitry path to transfer the timing signal for transmission; and an input/output port coupled to the isolation circuit and the transmit circuitry path, whereinthe transmit circuitry path comprises a protected controlled latency circuit coupled to an isolation circuitry, the transmit circuitry path is to protect against signals received through the transmit circuitry path and control signal propagation latency, the isolation circuit is to isolate the transmit circuitry path from voltage received at an output from the transmit circuitry path during transmission mode, the protected controlled latency circuit comprises a buffer and current regulating circuitry coupled in parallel with at least N other sets of a buffer and other current regulating circuitry, an RC time constant of the transmit circuitry path is based on a value of N, and the current regulating circuitry is to reduce a level of received current at the buffer due a voltage applied at the input/output port during the transmission mode. 2. The apparatus of claim 1 , wherein the transmit circuitry path is to provide single-digit nanosecond rise time for a transmitted timing signal. 3. The apparatus of claim 1 , wherein the receive circuitry path comprises one or more of:current regulating circuitry connected between the isolation circuit and the second circuitry and second current regulating circuitry connected between the second circuitry and the circuitry to generate the timing signal based on the received signal. 4. The apparatus of claim 1 , wherein the primary-secondary clock scheme comprises Institute of Electrical and Electronics Engineers (IEEE) 1588 Precision Time Protocol (PTP). 5. The apparatus of claim 1 , comprising a network interface coupled to the receive circuitry path and the transmit circuitry path, the network interface to transmit and receive data packets. 6. The apparatus of claim 1 , comprising a rack, server, or data center, wherein the rack, server, or data center include the circuitry to generate the timing signal based on the received signal, the receive circuitry path, and the transmit circuitry path. 7. A method comprising:performing time synchronization using a circuit that provides protection against circuit damage from misconfigured port use of signal transmission during receive mode and signal receipt during transmit mode and commensurate with providing the protection, the circuit controlling latency of a transmit signal, wherein the circuit comprises:an input/output port; a first circuitry to generate a timing signal by calibration of the timing signal and a received signal and based on a primary-secondary clock scheme, wherein the received signal comprises a 1 PPS signal, a 10 MHz signal, or other frequency clock signal; a receive circuitry path to transfer the received signal to the first circuitry, wherein the receive circuitry path comprises an isolation circuit coupled to the input/output port and second circuitry to receive different voltage level ranges of the received signal; a transmit circuitry path to transfer the timing signal for transmission from the input/output port, whereinthe transmit circuitry path comprises a protected controlled latency circuit coupled to an isolation circuitry, the transmit circuitry path is to protect against signals received through the transmit circuitry path and provide a controlled signal propagation latency and the isolation circuit is to isolate the transmit circuitry path from voltage received at an output from the transmit circuitry path during transmission mode, and a current regulating circuitry is to reduce a level of received current at a buffer based on a voltage applied at the input/output port during the transmission mode. 8. The method of claim 7 , wherein the transmit circuitry path comprising:a set of a buffer in series with a current regulating circuitry coupled in parallel with at least N other sets of a buffer in series with a current regulating circuitry, wherein a number N adjusts an RC time constant of the transmit circuitry path. 9. The method of claim 7 , wherein the receive circuitry path comprises:a current regulating circuitry positioned between the isolation circuit and the second circuitry to receive different voltage level ranges of the received signal; and a second current regulating circuitry between the circuitry to receive different voltage level ranges of the received signal and the circuitry to generate the timing signal based on the received signal. 10. A system comprising:at least one memory; at least one processor coupled to the at least one memory; and a network interface comprising a timing synchronization system, wherein the timing synchronization system comprises:an input/output port; a transmit circuitry path that is to protect against signals received through the transmit circuitry path and a control signal propagation latency; and a receive circuitry path, wherein:the timing synchronization system comprises a circuitry to generate a timing signal by calibration of the timing signal and a received signal from the input/output port and based on a primary-secondary clock scheme, wherein the received signal comprises a 1 PPS signal, a 10 MHz signal, or other frequency clock signal, the receive circuitry path to transfer the received signal to the circuitry, wherein the receive circuitry path comprises an isolation circuit coupled to an input/output port and second circuitry to receive different voltage level ranges of the received signal; the transmit circuitry path to transfer the timing signal for transmission, wherein the transmit circuitry path comprises a protected controlled latency circuit coupled to an isolation circuitry, wherein the transmit circuitry path is to protect against signals received through the transmit circuitry path and provide a controlled signal propagation latency and the isolation circuitry is to isolate the transmit circuitry path from voltage received at an output from the transmit circuitry path during transmission mode. 11. The system of claim 10 , wherein the transmit circuitry path comprises:a set of buffer in series with a resistor coupled in parallel with at least N other sets of buffer in series with a current regulating circuit, wherein a number N effects an RC time constant. 12. The system of claim 11 , wherein an RC time constant of the transmit circuitry path is based on a value of N. 13. The system of claim 11 , wherein, within the set of buffers, a current regulating circuitry comprises a resistor to reduce current level received at a buffer due a voltage applied at an input/output port during transmission mode. 14. The system of claim 10 , wherein the receive circuitry path comprises one or more ofcurrent regulating circuitry connected between the isolation circuit and the second circuitry and second current regulating circuitry connected between the second circuitry and the circuitry to generate the timing signal based on the received signal.
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