FIG. 2 depicts an example time synchronization system. The system can receive signals via an SMA port 202 and/or transmit a signal to an SMA port 202. Control logic 204 enables either receive or transmit paths, while preventing both transmit and receive paths from being enabled simultaneously. An SDP provided by system controller 250 can be a form of General Purpose Input/Output (GPIO) signal that is used to configure control logic 204 to enable a receive or transmit path. Example descriptions of receive and transmit paths are provided with respect to respective FIGS. 3A and 3B. Various embodiments provide for receipt of a signal from an SMA port 202 that permits multi-voltage level shifting using level shifter 214 and a ?50 ohm termination resistor 212 without interfering with a transmission path. Various embodiments provide for transmission of a signal to an SMA port 202 with circuit protection from misconfiguration and bus contention due to receipt of a signal during a transmission interval. Various embodiments provide a protected controlled latency circuit with configurable propagation delay and rise time of the time synchronization signal even in the case of additional load capacitance (e.g., from PCB traces, board components, or connected cables (e.g., twisted pair)).
