白丝美女被狂躁免费视频网站,500av导航大全精品,yw.193.cnc爆乳尤物未满,97se亚洲综合色区,аⅴ天堂中文在线网官网

Bi-directional buffer with circuit protection time synchronization

專利號(hào)
US12200089B2
公開(kāi)日期
2025-01-14
申請(qǐng)人
Intel Corporation(US CA Santa Clara)
發(fā)明人
April E. Fisher; Benjamin Cheong; Kevin Bross; Manishkumar T. Rana; Andrew M. Monk
IPC分類
H04L7/00
技術(shù)領(lǐng)域
or,tx,signal,sdp,sma,can,resistor,path,transmit,circuitry
地域: CA CA Santa Clara

摘要

Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.

說(shuō)明書

FIG. 3A depicts an example of a receive portion of the system. Various embodiments include an isolation switch 210 between SMA input 202 and termination resistor 212. Isolation switch 210 can be implemented as a FET bus switch. Termination resistor 212 at the input of level shifter 214 is used to avoid transmission line reflections and can be approximately a ?50 ohm pull-down resistor. Note any current regulating circuitry or resistor can be implemented as resistor devices, one or more metal-oxide-semiconductor field-effect (MOSFET) or FET transistors, or other logic. Termination resistor 212 is not in a signal path during transmission from SMA port 202 because during signal transmission (described later), level shifter 214 is isolated and disconnected from the transmit path.

權(quán)利要求

1
微信群二維碼
意見(jiàn)反饋