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Bi-directional buffer with circuit protection time synchronization

專(zhuān)利號(hào)
US12200089B2
公開(kāi)日期
2025-01-14
申請(qǐng)人
Intel Corporation(US CA Santa Clara)
發(fā)明人
April E. Fisher; Benjamin Cheong; Kevin Bross; Manishkumar T. Rana; Andrew M. Monk
IPC分類(lèi)
H04L7/00
技術(shù)領(lǐng)域
or,tx,signal,sdp,sma,can,resistor,path,transmit,circuitry
地域: CA CA Santa Clara

摘要

Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.

說(shuō)明書(shū)

40 ohm rise time calculation Series Resistance (ohms) 40 Load Capacitance (pF) 350 Time Constant (ns) 14 Vsignal 3.3 % Rise Time 0.7 Voh 2.31 Rise Time to Voh (ns) 16.85562

權(quán)利要求

1
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