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Bi-directional buffer with circuit protection time synchronization

專利號
US12200089B2
公開日期
2025-01-14
申請人
Intel Corporation(US CA Santa Clara)
發(fā)明人
April E. Fisher; Benjamin Cheong; Kevin Bross; Manishkumar T. Rana; Andrew M. Monk
IPC分類
H04L7/00
技術領域
or,tx,signal,sdp,sma,can,resistor,path,transmit,circuitry
地域: CA CA Santa Clara

摘要

Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.

說明書

For a misconfiguration, scenario 12 represents a scenario where the time synchronization system is unpowered but a signal is received at the SMA port. On the transmit path, isolation circuitry 228 and on the receive path, isolation switch 210 can prevent damage to the time synchronization system by scenario 12.

For a misconfiguration, scenario 17 represents a scenario where a receive path is enabled but there a voltage at the SMA port. This causes a device that can handle 5.5V and translate it to the 3.3V I/O voltage of the system controller 250, which is done with the level shifter 214.

TABLE 2 User Configurations Path

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