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Bi-directional buffer with circuit protection time synchronization

專利號
US12200089B2
公開日期
2025-01-14
申請人
Intel Corporation(US CA Santa Clara)
發(fā)明人
April E. Fisher; Benjamin Cheong; Kevin Bross; Manishkumar T. Rana; Andrew M. Monk
IPC分類
H04L7/00
技術(shù)領(lǐng)域
or,tx,signal,sdp,sma,can,resistor,path,transmit,circuitry
地域: CA CA Santa Clara

摘要

Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.

說明書

Results Enabled Voltage at Current Controller via Controller at Current Timing Control SDP OpAmp Sourced/Sinked Link Partner SDP Logic Voltage (must be Output by Controller Scenario Setup Setup SDPs at SMA <= 3.3 V) Resistor (must be <= 12 mA) Valid Configurations

權(quán)利要求

1
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