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Bi-directional buffer with circuit protection time synchronization

專(zhuān)利號(hào)
US12200089B2
公開(kāi)日期
2025-01-14
申請(qǐng)人
Intel Corporation(US CA Santa Clara)
發(fā)明人
April E. Fisher; Benjamin Cheong; Kevin Bross; Manishkumar T. Rana; Andrew M. Monk
IPC分類(lèi)
H04L7/00
技術(shù)領(lǐng)域
or,tx,signal,sdp,sma,can,resistor,path,transmit,circuitry
地域: CA CA Santa Clara

摘要

Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.

說(shuō)明書(shū)

10 Output Output Rx Path ??0 V ??0 V 0 0 (LP Tx (SDP Tx low = 0 V) low = 0 V) 11 Output Output Rx Path ??0 V 3.3 V 0 3.3 V/R (LP Tx (SDP Tx low = 0 V) high = 3.3 V) 12 Output Off Off 5.5 V ??0 V 0 0 (LP Tx high = 5.5 V) 13 Output Input Tx Path 5.5 V ??0 V 5.5 V/R 0 (LP Tx high =

權(quán)利要求

1
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